SOC Physical Design Static Timing Analysis Engineer

Job Title

SOC Physical Design Static Timing Analysis Engineer

Role Summary

The engineer will perform SOC-level static timing analysis (STA) and timing closure for complex System-on-Chip (SoC) designs, working with clocking, architecture, DFT and full-chip teams to meet performance, power, and functional requirements.

Primary responsibilities include timing analysis and optimization, timing constraint generation and verification, clock network design, and developing methodologies and flows to improve physical design execution and timing signoff.

Experience Level

Senior — expects strong domain experience with at least 7+ years of SOC-level static timing analysis and timing closure work, plus additional experience (3+ years) with timing constraints, physical-design optimization, and relevant tooling.

Responsibilities

The role focuses on STA, timing optimization, clocking, and methodology development for SoC physical design.

• Perform SOC-level timing analysis, rollups, and timing closure to meet functional and performance goals.
• Generate, verify, and adapt timing constraints; diagnose and fix timing violations at block and chip level.
• Design and optimize clock networks for functionality, performance, and power efficiency.
• Define PVT corners and alignment with product planning and binning strategies for timing analysis.
• Collaborate with clocking, architecture, DFT, logic, and full-chip teams on integration and timing guidelines.
• Develop tools, flows, and methodologies to improve timing models, physical design execution, and STA efficiency.

Requirements

Must-have skills and experience for initial consideration; preferred items listed separately.

• Must-have: 7+ years technical proficiency in SOC-level static timing analysis, timing closure, and clock network design.
• Must-have: 3+ years experience in timing-constraint adaptation, physical-design optimization techniques, and timing budgeting.
• Must-have: Proficiency with industry-standard timing analysis, extraction, and physical-design tools.
• Must-have: Familiarity with TCL scripting for automation and timing flows.
• Nice-to-have: Experience with SoC clocking methodologies, DFT architecture knowledge, and development of high-performance physical-design flows.
• Nice-to-have: Strong cross-team collaboration and technical communication skills.

Education Requirements

Bachelor's degree with 8+ years, Master’s degree with 6+ years, or PhD with 4+ years in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; equivalent practical experience is accepted and requirements may be met via a combination of industry experience, internships, coursework, or research.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.