Senior Staff Engineer, Digital IC Build Flow and Methodology

Job Title

Senior Staff Engineer, Digital IC Build Flow and Methodology

Role Summary

Deliver and maintain scalable build scripts, front-end methodology, and orchestration for complex digital IC designs (block, subsystem, full-chip, and multi-chip). The role sits with the digital/methodology team and partners closely with RTL, DV, methodology, and infrastructure teams to improve developer productivity, correctness, and flow performance.

This is a hands-on engineering role focused on build performance, CI/pre-submit flows, integration of EDA tools, and driving adoption through documentation and training.

Experience Level

Senior — typically 8+ years in ASIC/SoC design, verification, or methodology roles (posting specifies 8+ years).

Responsibilities

Primary responsibilities include developing and owning build infrastructure and methodology for front-end design and verification.

• Design, implement, and maintain build flows for block, subsystem, full-chip, and multi-chip simulations.
• Develop and own build scripts and orchestration for compile, elaboration, simulation, and regression workflows.
• Improve build performance via dependency analysis, incremental builds, caching, and flow optimization.
• Define and evolve front-end methodology standards and best practices.
• Architect and enhance CI / pre-submit verification flows to improve quality and turnaround time.
• Integrate and support industry EDA tools within scripted flows.
• Debug complex infrastructure and build-system issues at scale.
• Collaborate with RTL, DV, methodology, and infrastructure teams and drive adoption through documentation and training.

Requirements

Must-have technical skills and experience:

• 8+ years of experience in ASIC/SoC design, verification, or methodology roles.
• Strong programming skills in Python and at least one of TCL, C/C++, or shell scripting.
• Experience with make-based or graph-based build systems and dependency-graph build tools.
• Practical understanding of front-end chip design flows and EDA toolchains.
• Experience debugging large-scale infrastructure and build-system issues.
• Strong problem-solving skills and ability to collaborate across multiple engineering teams.

Nice-to-have / preferred:

• Experience with next-generation or programmable build flows and Bazel-like systems.
• Familiarity with CI systems such as Jenkins and compute-farm environments.
• Experience with multi-chip or chiplet-based designs and mentoring junior engineers.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (as stated in the posting). Equivalent practical experience may be considered where applicable.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.