SoC Logic Design Engineer - RTL/Verilog & IP Integration

Job Title

SoC Logic Design Engineer — RTL/Verilog & IP Integration

Role Summary

Design and deliver RTL for System-on-Chip subsystems and integrate third-party and internal IP blocks. Work on RTL creation, verification handoff, and interface definition within an SoC engineering team.

Experience Level

Mid-level. Specific years of experience not specified in the source posting.

Responsibilities

Deliver RTL and ensure correct integration of IP into SoC designs; collaborate with verification, synthesis, and IP teams.

• Write synthesizable RTL in SystemVerilog/Verilog for SoC components.
• Integrate internal and third-party IP and define interface protocols.
• Perform RTL code reviews and static quality checks.
• Create and run unit and integration-level simulations; support verification activities.
• Support synthesis and timing-closure readiness for implementation teams.
• Debug RTL issues and assist with pre- and post-silicon triage.
• Produce design documentation and participate in design reviews.

Requirements

Key technical skills and experience required or strongly preferred.

• Must-have: Proficiency in SystemVerilog and Verilog for RTL design.
• Must-have: Experience with RTL design and IP integration in SoC or ASIC projects.
• Must-have: Ability to collaborate with external IP providers and cross-functional engineering teams.
• Nice-to-have: Experience with simulation and verification flows, synthesis, and timing closure.
• Nice-to-have: Familiarity with verification methodologies (e.g., UVM) and scripting for automation (Python, Tcl).

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field is required.

About the Company

Company: BlackCube Labs

Technology company recruiting SoC and hardware engineers to develop System-on-Chip designs, RTL/Verilog, and IP integration. Focuses on advanced semiconductor and SoC development and engineering services.