SOC Engineering Staff Engineer - Physical Design

Job Title

SOC Engineering Staff Engineer - Physical Design

Role Summary

You will be responsible for the complete physical design implementation using RTL2GDSII flows for advanced process nodes. Your role involves ensuring successful tape-outs, optimizing designs for performance and power targets, and collaborating with cross-functional teams.

Experience Level

Level - Senior

Responsibilities

• Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm).
• Execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA).
• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.
• Utilize and optimize Synopsys EDA tools like Design Compiler, IC Compiler II, and PrimeTime.
• Develop and maintain automation scripts in Python, PERL, TCL, or relevant languages.
• Contribute to the continuous improvement of design methodologies and best practices.

Requirements

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or a related field.
• 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).
• Experience with RTL2GDSII flows, synthesis, timing optimization, STA, EMIR, and physical verification.
• Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.
• Strong scripting and automation skills using Python, PERL, TCL, or similar languages.
• Solid understanding of timing constraints and timing closure techniques.

Education Requirements

Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or a related field.