SOC Engineering Staff Engineer (Physical Design)

Role Summary

We are looking for a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and solid experience in advanced technology nodes. You will own and deliver complex designs while ensuring successful tape-outs in fast-paced environments.

Experience Level

5+ years of relevant experience in physical design, especially in advanced technology nodes such as 7nm, 5nm, or even 3nm.

Responsibilities

• Independently drive full RTL2GDSII physical design implementation for advanced process nodes.
• Execute synthesis, place & route, clock tree synthesis, timing optimization, and static timing analysis to meet specific performance and power targets.
• Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.
• Collaborate with cross-functional teams to resolve design challenges and ensure quality.
• Utilize and optimize Synopsys EDA tools to deliver silicon solutions.
• Develop automation scripts in Python, PERL, or TCL to improve workflow efficiency.
• Contribute to the continuous improvement of design methodologies and mentor junior engineers.

Requirements

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or a related field.
• Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.
• Strong scripting and automation skills using Python, PERL, TCL, or similar languages.
• Solid understanding of timing constraints and floor-planning techniques.

Education Requirements

Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in relevant engineering fields.