SoC Engineering Senior Engineer

Job Title

SoC Engineering Senior Engineer

Role Summary

Senior RTL/SoC designer working on block-level RTL and subsystem integration within the Solutions group. The role focuses on producing synthesizable, timing-closure-ready RTL and collaborating with verification, DFT, and physical design teams to deliver customer SoC projects to silicon.

This is a hybrid position based in Gilbert, AZ, working with global teams on automotive, aerospace, defense, and high-performance compute designs.

Experience Level

Senior - the posting specifies 3 to 4 years of hands-on ASIC or FPGA RTL design and implementation experience.

Responsibilities

Primary responsibilities include RTL development, quality checks, and cross-team collaboration to achieve timing and delivery goals.

• Write and review Verilog, SystemVerilog, or VHDL RTL for block-level designs (state machines, pipelines, FIFOs, memory controllers) from micro-architecture specs.
• Run RTL quality checks: linting, CDC/RDC analysis, and synthesis; iterate to ensure clean handoff to physical design.
• Collaborate with verification engineers to debug testbench failures, close coverage gaps, and refine corner-case behavior.
• Work with physical design teams to resolve timing, optimize logic for synthesis, and support timing closure from netlist to signoff.
• Implement and validate standard interfaces such as AXI, APB, AHB, I2C, and SPI within SoC subsystems.
• Automate repetitive tasks using scripting (Python, Tcl, shell) to improve design flow efficiency.
• Participate in design reviews and clearly communicate design decisions and tradeoffs across time zones.

Requirements

Must-have technical skills and experience; followed by preferred skills.

• 3 to 4 years of hands-on ASIC or FPGA RTL design, implementation, and debug (removed degree details to Education Requirements section).
• Strong proficiency in Verilog, SystemVerilog, or VHDL for registers, pipelines, state machines, memories, and FIFOs.
• Working knowledge of the ASIC design flow from micro-architecture through RTL development, synthesis, and timing closure.
• Experience using simulators, lint tools, CDC/RDC analysis, synthesis tools, and static timing analysis (tool-specific experience preferred).
• Familiarity with AXI/APB/AHB and other standard protocols; ability to implement and debug interface logic.

• Nice-to-have: experience with PCIe, DDR, Ethernet, SystemVerilog assertions, C++ or Python for verification/scripting, low-power design and UPF, DFT, Git-based workflows, formal tools, or AI-assisted engineering/code-generation tools.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (as listed in the posting). No alternate-equivalent-experience language provided.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.