SOC Engineer - Synthesis and Timing

Role Overview

We are seeking SOC engineers to work on ASIC/SOC projects based in Ho Chi Minh City, Vietnam. The SOC engineer will collaborate on projects utilizing Synopsys EDA tools to deliver system design solutions and contribute to both turnkey projects and customer advisory services.

Position Summary

As a SOC engineer, you will play a crucial role in synthesizing designs, performing timing analysis, and ensuring the overall integrity of the design process. You will be part of a dedicated service project team aimed at addressing and solving customer-specific challenges.

Experience Level

The ideal candidate should have 6 to 12 years of relevant experience in ASIC/SOC design, showcasing a comprehensive understanding of synthesis, timing closure, and related disciplines.

Key Responsibilities

Your responsibilities will include:

• Synthesis of design
• Logic Equivalence Checking (LEC)
• Layout Design Rule Checking (LDRC)
• Gate-level Comparison Analysis (GCA)
• Static Timing Analysis (STA)
• PTPX implementation

You will also innovate and independently implement solutions to complex problems while collaborating with cross-functional teams to enhance tool and IP solutions.

Required Qualifications

Candidates should possess:

• Proficient understanding of ASIC/SOC design and synthesis processes
• Knowledge of synthesis, LEC, and STA flow
• Familiarity with low-power, high-performance design techniques, particularly at advanced nodes (under 12nm)
• Experience with RTL, DFT, LDRC, GCA, and scripting languages (TCL, Perl, Python)
• Strong English communication skills and a readiness to engage with customers

Education Requirements

A Bachelor’s or Master's degree in Electrical Engineering or a related field is required.