SoC Design Verification Engineer

Job Title

SoC Design Verification Engineer

Role Summary

Work on pre-silicon RTL verification for wireless SoC designs within a multidisciplinary silicon development team. The role owns verification scope from test planning through coverage closure and signoff at block, subsystem, and full-SoC levels.

Collaborate with architects, RTL designers, firmware engineers, and validation teams to build reusable, metric-driven verification environments and to apply simulation, formal, and AI-assisted techniques where appropriate.

Experience Level

Mid-level. The posting does not specify a required number of years; candidates are expected to have practical, hands-on verification experience across the verification cycle.

Responsibilities

Primary responsibilities include planning and executing pre-silicon verification and improving verification methodology and automation.

• Develop verification plans from specifications and partner with architects/designers early in the cycle.
• Implement reusable block/IP and subsystem-level UVM testbenches and support SOC integration.
• Create directed and constrained-random tests; define and drive coverage models to closure.
• Debug functional failures and manage bug tracking through resolution.
• Verify low-power intent (e.g., using UPF) within assigned scope.
• Verify end-to-end subsystem and top-level traffic flows (Wi‑Fi, Bluetooth, peripherals, interconnects).
• Apply formal methods where appropriate and contribute to automated regression flows.
• Explore and apply AI-assisted verification techniques to improve productivity.
• Participate in verification reviews and support post-silicon bring-up as needed.

Requirements

Must-have technical skills and practical verification experience; preferred items listed separately.

• Hands-on experience across the verification cycle: test planning, testbench implementation, test creation and debug, and coverage closure.
• Strong SystemVerilog and Verilog skills and working knowledge of UVM.
• Proven debugging and problem-solving skills in constrained-random verification environments.
• Understanding of digital logic design, SoC architecture, and microarchitecture.

Nice-to-have:

• Experience taking an ASIC/SoC from concept through tape-out.
• Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in UVM.
• Experience with Wi‑Fi or Bluetooth SOC verification or knowledge of wireless protocols.
• Low-power verification, UPF, boot sequencing, and HW/FW interaction experience.
• Experience with SVA and/or formal tools (e.g., JasperGold).
• Experience defining coverage space and writing coverage models.
• Embedded CPU verification and programming in C/C++ or assembly.
• Scripting in Python or Perl; interest in applying AI/ML to verification workflows.
• Strong teamwork and communication skills.

Education Requirements

Bachelor's degree required. The posting does not specify a field of study or list alternative equivalent-experience language.

About the Company

Company: Apple

Headquarters: Cupertino, California, United States

Apple is a multinational technology company that designs, manufactures, and sells consumer electronics, software, and online services. Known for its innovative products such as the iPhone, Mac computers, and iPad, Apple emphasizes a strong commitment to high-quality design and user experience.