SoC Design Verification Engineer

Job Title

SoC Design Verification Engineer

Role Summary

Join MatX's hardware verification team to develop and execute verification for SoC blocks, subsystems and full-chip silicon for high-performance GenAI products. The role focuses on building scalable verification methodology, creating testbenches and driving verification to sign-off for tapeout.

Experience Level

Mid-level — approximately 3–7 years of relevant verification or silicon experience (title and compensation bands indicate opportunities at multiple career levels).

Responsibilities

Deliver verification artifacts and drive closure from block to system level.

• Design and implement verification testbenches, tests and related artifacts to achieve structural and functional coverage closure.
• Contribute to and evolve a scalable verification methodology across blocks, subsystems and full-chip/system validation.
• Own verification execution for assigned subsystems and chip-level features.
• Plan and lead intermediate and sign-off reviews for verification test plans, execution status and closure toward milestones (design freeze, tapeout).
• Develop portable tests and drivers that support silicon validation and post-silicon debug.

Requirements

Must-have technical skills and constraints for the role.

• Concept-to-silicon verification experience: driving verification from architecture/design specification through production silicon.
• Proficient with SystemVerilog and scripting/programming languages such as Python and C/C++; experience with Bluespec is valuable.
• Production experience with advanced verification methodologies (UVM) and assertion-based verification; formal and simulated verification experience required.
• Experience creating portable verification tests and drivers applicable to silicon validation and post-silicon debug.
• Strong understanding of silicon micro-architecture and design concepts relevant to high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity and memory management.
• Ability to participate in verification sign-off activities and to deliver verification artifacts on schedule.
• Must be authorized to work in the United States and able to work from MatX Mountain View offices Tuesdays–Thursdays.
• Role requires compliance with U.S. export control laws; employment contingent on ability to perform duties without a special export license.

Nice-to-have:

• Familiarity with emulation and prototyping platforms and methodologies.
• Hands-on experience with silicon debug and bring-up.

Education Requirements

Not specified.

About the Company

Company: MatX

Headquarters: Mountain View, California, USA

MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.