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SoC Clock, Power, Reset Design Lead

Arm
Full-time
Remote friendly (Cambridge, United Kingdom)
Worldwide
Level - Senior

Role Summary

Arm is seeking an experienced SoC Clock, Power and Reset Lead to drive development for our next-generation SoCs. You will collaborate closely with architecture, verification, and implementation engineering teams to develop robust solutions that meet power, performance, and area expectations across diverse workloads and deployment environments.

Experience Level

10+ years of experience in SoC development, with a focus on clocking, power, or reset.

Responsibilities

As a lead design engineer, your responsibilities include:

  • Working with SoC architects to understand system and subsystem requirements and develop design specifications that meet Power, Performance, and Area goals.
  • Writing SoC-level design micro-architecture specifications, developing RTL, fixing bugs, running design checks, and contributing to the generation of implementation constraints.
  • Collaborating with subsystem design leads to communicate clock, reset, and power strategies and review micro-architectural designs.
  • Reviewing test plans and helping debug design issues with the verification lead.
  • Identifying and defining next-generation IPs and methodologies with clock, power, and reset architects to improve system-level power and performance.
  • Improving and evolving design methodologies, flows, and guidelines.
  • Mentoring and supporting junior team members to ensure successful project execution.

Requirements

Key qualifications include:

  • Master’s degree (or higher) in Computer Engineering, Computer Science, Electrical Engineering, or a related discipline.
  • Deep knowledge of system architecture and micro-architecture with a proven track record of making SoC-level micro-architectural trade-offs.
  • Experience with power management and low-power design techniques.
  • Good understanding of digital hardware design and Verilog HDL.
  • Real-world experience planning and implementing clock, power, and reset domains in large SoCs.

Education Requirements

Master’s degree (or higher) in Computer Engineering, Computer Science, Electrical Engineering, or related discipline.