SoC Chip Lead

Job Title

SoC Chip Lead

Role Summary

Senior technical lead responsible for end-to-end SoC and multi-chip-module (MCM) development at the San Jose site, owning chip tapeout, signoff, and production release. The role coordinates cross-functional engineering teams (architecture, RTL, software, verification, packaging) to deliver chiplet-based and 2.5D/3D packaged solutions.

Experience Level

Senior - requires extensive industry experience (posting specifies 20+ years of FPGA/SoC design experience).

Responsibilities

Primary accountabilities and technical leadership expectations.

• Lead development of MCMs and chiplet-based SoCs using 2.5D/3D advanced packaging across multiple program generations.
• Own chip tapeout and chip signoff with full accountability for chip quality and production release.
• Translate product requirements into technical priorities, tradeoffs, and execution plans across distributed teams and sites.
• Partner with architects, RTL, and software teams to evaluate architecture tradeoffs and guide hardware design decisions.
• Perform cycle-approximate performance modeling to support architectural exploration and early software enablement.
• Quantify system-level tradeoffs across compute, memory bandwidth, and on-chip interconnect to shape reference architectures.
• Own system-level debug including floorplanning, power distribution, clocking, timing closure, and SI/PI.
• Define and execute DFx and manufacturing test strategies from IP to chip (scan, BIST, manufacturing test).
• Engage with IP vendors, manage IP roadmap, and conduct competitive benchmarking.
• Present technical status and roadmaps to executive leadership; identify new markets and growth opportunities.
• Apply agentic AI methodologies to accelerate design execution and scaling of workflows.

Requirements

Must-have technical skills, experience, and leadership capabilities.

• Established track record leading SoC/Fabric/FPGA programs from concept through tapeout and production release.
• Expertise in SystemVerilog, RTL synthesis, and static timing analysis.
• Deep domain knowledge in high-speed interfaces, system interconnects, processor subsystems, and advanced packaging/chiplet architectures.
• Proven ability to own system-level functional and performance modeling with RTL correlation and emulation-based pre-silicon validation.
• Experience debugging complex systems using verification, emulation, and system validation techniques.
• Experience defining and owning DFx methodologies (scan, BIST, test from IP to chip level).
• Demonstrated leadership of geographically distributed, cross-functional engineering teams.
• Strong written and verbal communication skills and experience presenting to executive-level audiences.

Education Requirements

Posting specifies BS, MS, or PhD in Electrical or Computer Engineering. The job also specifies 20+ years of FPGA/SoC design experience.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.