SMTS Verification Engineering

Role Summary

The Principal Verification Engineer will report to the Director of Verification and play a critical role in product development, specifically focusing on defining and executing verification plans for DDR memory interface products.

Experience Level

Senior level; candidates should have 5-8 years of experience with a Master's degree in Electrical Engineering or 5+ years with a PhD.

Responsibilities

The main responsibilities include:

• Create digital verification plans using datasheets and collaborate with engineers and customers.
• Implement digital test-benches in SystemVerilog and UVM.
• Debug issues and track bugs, functional coverage, and RTL code coverage.
• Work in a dynamic R&D group contributing to methodology development.
• Mentor junior engineers.

Requirements

Applicants must meet the following requirements:

• MS in Electrical Engineering or PhD with relevant experience.
• Significant experience with System Verilog or Verilog and UVM methodology.
• Experience in Analog/Mixed-signal products (DDR, HSS, PCIE, etc.) is highly desirable.
• Strong knowledge of ASIC verification flow/software tools.
• Familiarity with scripting and Linux/Unix environments.
• Excellent English communication skills and ability to work in cross-functional teams.

Education Requirements

A Master's degree in Electrical Engineering or a PhD in Electrical Engineering is expected.

About the Company

Company: Rambus

Headquarters: Sunnyvale, California, USA

Rambus is a global leader in advanced semiconductor and technology solutions, specializing in enhancing data access and improving performance in computing, networking, and storage applications. The company is known for its innovative IP and solutions in memory, security, and interface technologies. With a strong focus on research and development, Rambus continues to push the boundaries of technology to meet the growing demands of the digital age.