SMTS Analog Design Engineer, Mixed-Signal PHY (Clocking & High-Speed I/O)

Job Title

SMTS Analog Design Engineer, Mixed-Signal PHY (Clocking & High-Speed I/O)

Role Summary

Member of Micron's Interface Pathfinding team responsible for designing custom analog/mixed-signal blocks with a primary focus on clocking for high-speed PHYs. Work spans specification, transistor-level simulation, layout collaboration, silicon bring-up, and documentation.

Small senior team environment delivering pathfinding analog architectures for high-speed die-to-die and short-reach interconnects on advanced CMOS nodes.

Experience Level

Senior level. The role expects significant industry experience; the posting specifies 10+ years of analog/mixed-signal IC design experience.

Responsibilities

Design and validate custom analog blocks and contribute to PHY analog architecture.

• Own schematic, simulation, and layout review for one or more custom analog blocks (clocking as primary focus).
• Define top-level analog architecture: clocking topology, signal-chain partitioning, power domains, and tradeoffs.
• Develop and maintain transistor-level simulation testbenches; run corner, Monte Carlo, and mismatch analyses.
• Specify clean analog-digital interfaces: signal naming, timing contracts, and boundary constraints.
• Collaborate with layout on matching, shielding, guard rings, and parasitic sensitivity.
• Support post-silicon characterization: correlate measurements to simulation and root-cause performance deltas.
• Author block-level specifications, simulation reports, and interface control documents.

Requirements

Must-have technical skills and relevant experience.

• 10+ years of analog/mixed-signal IC design experience with at least one tape-out in a primary ownership role.
• Deep transistor-level implementation experience in advanced CMOS for clocking circuits (PLL, DLL, CDR).
• Strong transistor-level simulation skills using HSpice or equivalent; comfortable with corner, Monte Carlo, and mismatch analysis.
• Solid understanding of jitter analysis (phase noise, period jitter, cycle-to-cycle jitter) and impact on link timing.
• Experience defining analog-digital interfaces, including timing contracts and digital control of analog parameters.
• Proven ability to work as a peer technical contributor on a small, cross-discipline team and produce written design documentation.

Nice-to-have:

• High-speed transmitter and receiver design experience (pre-emphasis, CTLE/DFE, samplers, impedance control).
• Familiarity with die-to-die PHY architectures (UCIe, AIB, BoW) and OTP/fuse-based calibration approaches.
• Experience with RNM or Verilog-AMS behavioral modeling and post-silicon characterization of eye diagrams, BER, and jitter.
• Prior experience in small pathfinding teams where analog architecture is developed rather than handed down.

Education Requirements

BS, MS, or PhD in Electrical Engineering or a related field; MS/PhD strongly preferred for this level. (Degree requirement stated in the posting.)

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.