Silicon Physical Design Engineer

Role Summary

This position focuses on the physical design implementation of multi-hierarchy low-power machine learning hardware at Meta, particularly related to advanced technology nodes. The role demands a strong background in ASIC design and a collaborative approach to work with hardware designers in optimizing compute blocks for efficiency.

Experience Level

The candidate should have significant experience, with a minimum of 8 years in ASIC Physical Design. Extensive knowledge of RTL to GDSII flow and working with advanced process technologies, particularly at 3nm or below, is essential.

Responsibilities

• Develop and manage physical design implementations for low-power ML hardware, including logic synthesis, floorplanning, and static timing analysis.
• Identify and resolve physical design challenges, proposing effective solutions.
• Work closely with ML architects to generate methodologies for optimizing the PPA of design blocks.
• Collaborate across disciplines on various initiatives from concept development to prototyping and production transition.
• Participate in domestic and international travel as required.

Requirements

Candidates must possess a Bachelor's degree in Computer Science, Computer Engineering, or a similar field, along with practical experience in ASIC design. Proficiency in using EDA tools and programming languages such as Python and TCL is also required.

Education Requirements

A Bachelor's degree in a relevant technical field is required. A Master's or PhD is preferred but not mandatory.