Silicon Packaging Design Engineer

Job Title

Silicon Packaging Design Engineer

Role Summary

Design and deliver silicon interposer and embedded bridge layouts and routing to meet performance, cost, and manufacturability goals. Work with silicon, technology development, and hardware teams to optimize package-level integration, pinout, and system-level performance.

Primary work involves physical layout, routing studies, DRC resolution, and using EDA tools to produce manufacturable package designs.

Experience Level

Mid-level. Experience guidance: approximately 2–3 years of relevant industry experience.

Responsibilities

The core responsibilities focus on physical design, collaboration, analysis, and documentation.

• Design and implement physical layout and routing of silicon interposers and embedded bridges.
• Perform substrate fit and routing studies to evaluate tradeoffs in performance, cost, and manufacturability.
• Collaborate with silicon, technology development, and hardware teams on silicon-package-board integration and pinout optimization.
• Propose rule updates and lead internal/external design reviews to validate feasibility.
• Analyze design data and resolve design rule checks (DRCs) to produce optimized, manufacturable designs.
• Use EDA tools to create and verify package layouts and ensure design robustness.
• Document design specifications and processes in the product lifecycle management system and close milestone requirements through reviews.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Proficiency with custom layout and auto-place-and-route EDA tools such as Virtuoso, Innovus, FusionCompiler, ICvalidator, and/or Calibre.
• Practical experience in silicon physical layout design, routing interconnects, and using review/verification tools.
• At least one of the following: analog/mixed-signal fundamentals for signal integrity and I/O, power distribution and power integrity assessments, or reliability requirements for interconnects.
• Ability to analyze tradeoffs and produce manufacturable designs that meet performance and cost targets.

Nice-to-have:

• Familiarity with industry silicon physical design methodologies and workflows.
• Experience optimizing silicon performance and conducting tradeoff studies for advanced packaging designs.
• Strong cross-disciplinary collaboration and clear technical communication skills.

Education Requirements

Bachelor's degree with 3+ years of experience or Master's degree with 2+ years of experience in Electrical Engineering, Computer Engineering, or a STEM-related field (as stated in the posting).

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.