Silicon Integration Design Engineer - Timing Model

Job Title

Silicon Integration Design Engineer - Timing Model

Role Summary

Work in the silicon integration and timing modeling team to create, verify, and deliver timing models that integrate IP blocks with FPGA software tools. The role focuses on timing arc definition, model generation from SPICE/STA data, and ensuring models meet tool requirements.

Experience Level

Senior — requires approximately 10 years of hardware integration design experience and demonstrated participation in full product development through tape-out of at least two products.

Responsibilities

Primary technical responsibilities:

• Collaborate with IP designers and the modeling team to align timing model requirements with FPGA tool specifications.
• Define timing arcs and constraints from IP functionality and deliver specifications to software teams.
• Perform quality checks on timing models and resolve issues such as missing timing arcs or clock information.
• Generate timing reference and full-chip timing models using SPICE simulations and STA reports.
• Compare and translate timing between proprietary formats and Liberty (.lib) format.
• Support schematic generation and SPICE-based simulation data collection.
• Provide inputs for power modeling and back-end timing methodologies.
• Document results and communicate issues to cross-functional teams.

Requirements

Key qualifications and skills — must-haves first followed by advantages.

• Approximately 10 years' experience in hardware integration design.
• Proven experience completing full product development through tape-out for at least two products.
• Strong knowledge of static timing analysis (STA), timing modeling, and timing arc definition.
• Proficient in SystemVerilog and synthesis flows.
• Experience with Cadence Virtuoso schematic generation and SPICE simulation.
• Familiarity with Liberty (.lib) timing format and translating between formats.
• Experience with floor-planning, power estimation, and back-end methodologies.
• Linux scripting and Python skills.
• Strong written and verbal communication skills; ability to collaborate across teams.
• Right to work in Malaysia.

Nice-to-have: experience with PrimeTime/Liberate, FPGA power modeling, PnR knowledge, and ability to use AI tools to analyze data.

Education Requirements

Not specified.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.