Silicon Design Validation, Senior Manager

Job Title

Silicon Design Validation, Senior Manager

Role Summary

Lead a validation organization responsible for post-silicon bring-up, characterization, and production release of advanced programmable logic products. Manage strategy, technical direction, and execution across analog, digital, and mixed-signal IPs to ensure product quality and performance.

The role combines hands-on technical oversight of bring-up and characterization with people leadership and cross-functional coordination (design, verification, manufacturing, test, quality, and applications).

Experience Level

Senior — typically requires 15+ years in silicon validation with 3–5 years in a leadership role.

Responsibilities

Lead the team and define execution for post-silicon validation and production qualification.

• Develop and oversee validation and characterization strategies for analog, digital, and mixed-signal IPs (SERDES, DDR, PLLs, DSPs, DPHY, I/O subsystems).
• Plan and provision bench hardware, software, and infrastructure required for validation and qualification.
• Drive silicon bring-up, debug, and root-cause analysis; coordinate lab activities and resources for timely issue resolution.
• Supervise creation of RTL test logic and FPGA-based test implementations to enable targeted validation.
• Charter datasheet parameter characterization, statistical analysis of measured data, and datasheet preparation.
• Coordinate cross-functional collaboration with design, verification, manufacturing, test, quality, and product teams.
• Lead customer-facing technical support for post-release issues and coordinate internal remediation.
• Foster a technical learning culture to upskill engineers on FPGA architectures and IP blocks.

Requirements

Core technical and leadership qualifications required for the role.

• Must-have: 15+ years of silicon validation experience and proven track record managing complex validation projects and cross-functional teams.
• Must-have: Deep expertise in high-speed SerDes characterization and protocol compliance testing (examples: PCIe, Ethernet, JESD204, MIPI D-PHY, USB, DisplayPort, HDMI).
• Must-have: Strong background in high-speed board design, signal integrity evaluation, and debug; hands-on experience with BERT, VNA, oscilloscopes, and protocol analyzers.
• Must-have: Proficient in Verilog/VHDL and FPGA design implementation using industry-standard flows; experience with FPGA-based emulation/prototyping.
• Must-have: Experience developing test automation using Python and/or Perl.
• Must-have: Familiarity with statistical analysis tools and methods (examples: JMP, R) for characterization data analysis.
• Nice-to-have: Experience with specific interfaces/protocols relevant to product lines and prior work on low-power programmable logic devices.
• Nice-to-have: Strong written and verbal communication skills and demonstrated ability to mentor and develop engineering teams.

Education Requirements

Master's or Bachelor's degree in Electrical Engineering.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.