Silicon Design-for-Test (DFT) Engineer

Job Title

Silicon Design-for-Test (DFT) Engineer

Role Summary

Join MatX's Hardware team to design and implement DFT solutions for high-performance silicon used in ML/AGI compute. Responsible for DFT implementation, PHY test and firmware bring-up, and enabling production test and debug flows across IP and SoC levels.

Work closely with verification, firmware, and test teams to move test programs from simulation to ATE and to improve test coverage and quality.

Experience Level

Mid-level — typically 3–7 years of relevant experience in silicon DFT, PHY testing, or related hardware test engineering.

Responsibilities

Primary responsibilities include design, integration, and validation of DFT features and PHY test flows.

• Design and develop test solutions for SERDES PHY: loopback, eye characterization, and margin testing.
• Integrate PHY IP DFT features into SoC: boundary scan, BIST interfaces, test-mode control, and pattern porting from IP to SoC.
• Develop and maintain firmware loading flows for PHY bring-up (SPI/JTAG-based), register initialization sequences, and debug support for test development.
• Execute block-level DFT insertion and verification: scan chain closure, ATPG pattern generation, and sign-off.
• Collaborate with verification, firmware, and test engineering to transition test programs from simulation to ATE.
• Investigate test escapes and drive continuous improvement of DFT coverage and test quality.

Requirements

Must-have skills and experience; a few desirable items listed as nice-to-have.

• Hands-on DFT implementation experience (MBIST, at-speed scan, scan compression).
• Strong knowledge of JTAG (IEEE 1149.1), IJTAG (IEEE 1687), and Streaming Scan Networks (SSN).
• Experience loading and validating PHY firmware via serial interfaces (SPI, I2C, or JTAG) and performing register map initialization.
• Proven experience integrating PHY DFT interfaces and analog test buses into SoC DFT architectures.
• Familiarity with EDA DFT tools such as Synopsys DFT Compiler, Mentor Tessent, or equivalents.
• Ability to work from MatX offices in Mountain View Tuesdays–Thursdays and to comply with U.S. export control requirements.
• Nice-to-have: system-level DFT access, hierarchical test access, test data compression, and multi-die/chiplet DFT experience.

Education Requirements

Not specified.

About the Company

Company: MatX

Headquarters: Mountain View, California, USA

MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.