Silicon Design Engineer

Role Summary

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s GPU and Memory System IP, resulting in no bugs in the final design.

Experience Level

Senior level position, requiring significant professional experience.

Responsibilities

Key responsibilities include:

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
• Build testbench and develop the Testbench component with UVM
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Build the directed and random verification tests
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

Requirements

Preferred experience includes:

• Proficient in IP level or Subsystem level verification
• Proficient in debugging firmware and RTL code using simulation tools
• Proficient in using UVM Methodology and testbenches
• Experienced with Verilog, System Verilog, SVA, C, and C++
• Developing UVM based verification frameworks and testbenches, processes and flows
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
• Good knowledge of DMA, Memory system, Cache
• Exposure to leadership or mentorship is an asset
• Hands-on working experience and knowledge of formal verification is preferred
• Scripting language experience: Perl, Ruby, Makefile, shell preferred

Education Requirements

Bachelor's degree with at least 7 years of work experience or a Master's degree with at least 5 years of work experience in computer engineering or Electrical Engineering.