SiCADA Intern - IC Design and Verification Teaching Assistant (VDM / ADV)
SynopsysRole Summary
The SiCADA Internship Program 2026 is seeking an IC Design & Verification Teaching Assistant specializing in Verilog Design Methodology (VDM) and Advanced Design Verification (ADV).
Experience Level
Internship level; no specific years of experience required.
Responsibilities
Key responsibilities include:
- Assist SiCADA instructor in developing VDM and ADV homework specifications.
- Review ADV course materials, including SystemVerilog Testbench and Universal Verification Methodology, and update course content.
- Serve as a teaching assistant for VDM and ADV courses, addressing student questions and grading assignments.
- Support SoC implementation course, particularly with Static Timing Analysis (STA) and UPF teaching assistance.
Requirements
Preferred qualifications include:
- Understanding of Verilog Design Methodology and Advanced Design Verification.
- Familiarity with SystemVerilog and Universal Verification Methodology.
- Ability to assist in course material development and student support.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
