Senior VLSI Integration Engineer

Role Summary

The NVIDIA System-On-Chip (SoC) group is looking for a top ASIC Engineer with a focus on SoC design automation, RTL integration, chip build and assembly, and padring design and verification.

Experience Level

7+ years of actual design experience in chip design.

Responsibilities

• Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).
• Work on a variety of functional and structural challenges including functional debug, physical design readiness, emulation, and resolving design quality issues.
• Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, and design quality checks.
• Take part in flows development and deployment.

Requirements

• B.SC./M.SC. in Electrical Engineering/Computer Engineering.
• Solid hands-on RTL design skills in System-Verilog.
• Proficiency in at least one scripting language like Python, Bash, or Tcl.
• A strong teammate with a passion for quality.
• Experience with delivery to physical design, emulation, firmware, and other stakeholders.

Education Requirements

B.SC./M.SC. in Electrical Engineering/Computer Engineering.