Senior VLSI Design Engineer - RTL / Verilog / SystemVerilog

Job Title

Senior VLSI Design Engineer - RTL / Verilog / SystemVerilog

Role Summary

Senior ASIC/VLSI Design Engineer on the digital/core design team for next-generation DSP and communication SoCs. The role focuses on translating algorithmic requirements into synthesis-friendly RTL, optimizing for power, performance, and area, and collaborating with verification, DFT, and backend teams.

Onsite position in Austin, TX, working with a Series D semiconductor company building high-speed, low-power silicon for AI and cloud connectivity.

Experience Level

Senior — typically 5+ years of ASIC/VLSI digital design experience.

Responsibilities

Core responsibilities include architecture, RTL implementation, and delivery of production-quality silicon blocks:

• Define micro-architecture and implement RTL in Verilog/SystemVerilog that is synthesis-friendly.
• Perform synthesis, timing analysis, and PPA optimization.
• Collaborate with verification, DFT, backend (place & route), and system teams for integration and sign-off.
• Participate in design reviews and defend architectural and implementation choices.
• Support IP/SoC integration, create interface documentation, and validate designs via simulation and waveform analysis.
• Debug pre- and post-silicon issues and iterate designs to resolve functional and timing failures.
• Contribute to design methodology improvements and effective tool usage.

Requirements

Must-have technical skills and experience (concise):

• 5+ years of ASIC/VLSI digital design experience.
• Proficiency in Verilog and SystemVerilog RTL coding and coding for synthesis.
• Solid understanding of the ASIC design flow: synthesis, linting, CDC, and SDC constraints.
• Experience with DFT techniques: scan insertion, ATPG, BIST.
• Strong debugging, analytical skills, and familiarity with simulation and waveform analysis.
• Ability to work onsite in Austin, TX and collaborate across cross-functional teams.

Nice-to-have:

• Experience with optical communication systems or high-speed Ethernet (100G+).
• Background in DSP-oriented hardware blocks and high-speed interfaces.
• Scripting skills (Python, Perl, TCL) for automation and flows.
• Experience with IP/SoC integration and system-level interfaces.
• Startup/entrepreneurial mindset and ability to work independently.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (as stated). No certifications were specified. Equivalent practical experience was not mentioned explicitly.

About the Company

Company: Macpower Digital Assets Edge