Senior Verification Engineer

Job Title

Senior Verification Engineer

Role Summary

Senior verification engineer for memory interface IP (DDR/HBM) on an ASIC mixed-signal design and verification team based in Porto. Responsible for verification strategy, building SystemVerilog/UVM testbenches, driving coverage closure, and debugging across digital and mixed-signal domains.

Experience Level

Senior — typically requires 5+ years of hands-on verification experience in ASIC or mixed-signal environments.

Responsibilities

Primary responsibilities include translating specifications into executable verification plans and delivering robust verification environments for high-speed memory interfaces.

• Write verification specifications and test plans for DDR and HBM memory interface IP.
• Design and implement SystemVerilog testbenches and UVM environments for functional, performance, and corner-case verification of mixed-signal ASICs.
• Develop and run test cases for protocol compliance, signal integrity, timing closure, and power-aware scenarios.
• Create and maintain behavioral models in Verilog/SystemVerilog to enable early verification.
• Drive coverage closure using functional, code, and assertion-based metrics; identify gaps and write directed tests for hard-to-reach scenarios.
• Debug failures across digital and mixed-signal domains and work with design engineers to root-cause issues in simulation and on silicon.
• Document verification environments, methodologies, and results for internal use and customer delivery.
• Mentor junior verification engineers and contribute to adoption of advanced methodologies such as formal verification and AI-driven test generation.

Requirements

Required and preferred technical skills and experience.

• 5+ years of hands-on verification experience in ASIC or mixed-signal design environments.
• Deep expertise in SystemVerilog and UVM methodology; proven ability to build complex testbenches from scratch.
• Strong Verilog skills for RTL analysis and behavioral modeling.
• Proficiency in scripting (Python, Perl, or Tcl) for automation and test infrastructure.
• Experience with Unix/Linux environments and industry-standard EDA simulation and debug tools.
• Experience debugging across digital and mixed-signal domains and collaborating with design teams.

Nice-to-have:

• Experience with high-speed memory protocols such as DDR, HBM, or DFI.
• Experience with formal verification tools and power-aware verification techniques.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field (as stated in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.