Senior Verification Engineer

Role Summary

The Senior Verification Engineer will be responsible for verifying complex SoC and subsystem designs. This role involves collaborating with design and architecture teams to meet functionality, quality, and coverage goals across multiple projects.

Experience Level

Senior level with 7–10+ years of experience in verification or similar roles.

Responsibilities

Key responsibilities include:

• Analyze architectural specifications and define verification requirements.
• Develop and maintain UVM-based verification environments.
• Create detailed test plans and develop corresponding test cases.
• Debug functional issues and contribute to root-cause analysis.
• Collaborate closely with design and architecture teams to align milestones and quality metrics.

Requirements

The following qualifications are required:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
• 7–10+ years of experience in verification or similar roles.
• Strong expertise in SystemVerilog and UVM.
• Familiarity with Linux and standard EDA tools.
• Thorough understanding of the pre-silicon design and verification flow.
• Excellent communication, documentation, and teamwork skills.

Education Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.

About the Company

Company: FortifyIQ

Headquarters: Remote

FortifyIQ specializes in providing cutting-edge solutions in high-performance digital design and verification. The company offers a range of roles focused on hardware design and engineering in a remote work environment, catering to the needs of the evolving tech industry.