Senior Validation Engineer - Static Timing Analysis

Role Summary

This position involves working as a Senior Validation Engineer focusing on Static Timing Analysis (STA). The role requires expertise in timing analysis methodologies and tools, primarily supporting integration and validation efforts in semiconductor designs.

Experience Level

The ideal candidate will be at a senior career level, with proven experience in semiconductor validation and STA methodologies.

Responsibilities

• Conduct in-depth static timing analysis to ensure the performance of various chip designs.
• Develop and implement validation plans for STA methodologies.
• Collaborate with design engineers to revise and improve timing performance.
• Review and interpret results to facilitate design decisions and optimizations.
• Provide expertise and guidance in the adoption of timing analysis tools and processes.

Requirements

The successful candidate should possess a solid understanding of semiconductor processes and timing analysis, with hands-on experience with relevant tools.

Education Requirements

A Bachelor’s or advanced degree in Electrical Engineering, Computer Science, or related fields is preferred.