Senior UVM Digital Verification Engineer

Job Title

Senior UVM Digital Verification Engineer

Role Summary

Member of Draper’s Digital Design Team responsible for designing and executing verification strategies for FPGA and ASIC digital and mixed-signal designs in domains such as embedded security, cryptography, signal and image processing, navigation, and communications.

Work includes testbench and VIP development, formal analysis, coverage closure, and mentoring within multidisciplinary teams to translate requirements into verified designs.

Experience Level

Senior-level. Typically requires 5–7 years of relevant experience in systems analysis or digital verification engineering.

Responsibilities

Key responsibilities include planning and executing verification activities, leading small teams, and delivering verified RTL and testbenches.

• Develop verification approaches, author and execute verification plans.
• Design and implement UVM agents and block-level/chip-level UVM testbenches.
• Instantiate and integrate VIP for industry-standard buses.
• Work with RTL designers to identify and resolve simulation issues.
• Implement covergroups and close code and functional coverage targets.
• Use formal analysis tools to augment simulation-based verification.
• Perform code reviews and mentor junior engineers; lead small teams (fewer than five).
• Identify program/system-level technical risks and drive mitigation strategies.
• Contribute to requirements translation, architecture decisions, and integration testing.
• Document results and present findings that support system-level trade-offs and decision-making.

Requirements

Must-have technical skills and experiences; concise list of preferred extras follows.

• 5–7 years of experience in systems analysis or digital verification engineering.
• Fluent in SystemVerilog, including SVA; recent experience with UVM/UVMF.
• Practical experience with at least one major simulator (Questa, Xcelium, or VCS).
• Experience with bus protocols such as DDR3/DDR4 and AMBA AXI.
• Strong constrained-random testing and coverage-driven verification skills; experience closing coverage targets.
• Experience using formal analysis tools as part of the verification flow.
• Scripting and automation skills (Python, Perl, Bash) and comfort working in Linux.
• Proven ability to mentor junior engineers and lead small teams.
• Ability to obtain and maintain a U.S. government security clearance.
• Excellent written and verbal communication, organization, and time-management skills.

Education Requirements

Bachelor's degree in Aerospace, Electrical, Mechanical, or other relevant engineering field required. Master's degree preferred. (The posting also requires 5–7 years of experience; equivalent practical experience not explicitly stated.)

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.