Senior UVM Digital Verification Engineer

Job Title

Senior UVM Digital Verification Engineer

Role Summary

The Senior UVM Digital Verification Engineer will develop verification strategies and execute verification for FPGA and ASIC designs across domains such as embedded security, cryptography, signal and image processing, navigation, and communications. The role contributes to verification planning, testbench development, and cross-disciplinary integration in a research and development environment.

This is a senior, hands-on engineering role with mentorship responsibilities; the position supports remote work.

Experience Level

Senior — requires approximately 5–7 years of relevant experience in systems analysis, digital verification, or related engineering work.

Responsibilities

Primary duties include technical leadership of verification activities and collaboration with designers and stakeholders to deliver verified digital hardware.

• Develop and own verification approaches and plans for block- and chip-level designs.
• Author, implement and run UVM/UVMF testbenches and verification environments.
• Create UVM agents for proprietary buses and integrate/instantiate VIPs for standard buses.
• Execute constrained-random tests, implement covergroups, and close functional and code coverage.
• Use formal analysis tools to augment simulation-based verification.
• Perform code reviews, debug simulation issues with RTL designers, and propose design improvements.
• Mentor and provide technical guidance to junior engineers; lead small teams.
• Identify system-level technical risks and develop mitigation strategies.

Requirements

Must-have technical skills, tools, and experience for successful performance in this role.

• 5–7 years of experience in systems analysis, digital verification, or related engineering roles.
• Fluent in SystemVerilog including SVA; recent, practical experience with UVM/UVMF.
• Familiarity with at least one major simulator (QuestaSim, Xcelium, or VCS).
• Experience with industry bus standards and protocols (examples: DDR3/DDR4, AMBA AXI).
• Strong grasp of constrained-random testing, coverage-driven verification, and coverage closure.
• Experience using formal analysis tools in verification flows.
• Proficiency with scripting for verification automation (Python, Perl, Bash) and working in Linux environments.
• Demonstrated ability to lead small teams and mentor junior engineers; strong written and verbal communication skills.
• Ability to obtain and maintain a U.S. government security clearance.

Nice-to-have:

• Experience integrating descriptive modeling tools with other simulators or simulation tools.
• Prior work on mixed-signal or multi-domain verification projects.

Education Requirements

Bachelor's degree in Aerospace, Electrical, Mechanical, or another relevant engineering field is required. A Master's degree is preferred.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.