Senior Static Timing Analysis (STA) Developer

Role Summary

The Senior Static Timing Analysis (STA) Developer will architect, design, and optimize advanced timing analysis engines for ASIC and FPGA design flows. This role focuses on delivering high-performance STA solutions for complex SoC designs.

Experience Level

Senior, with a requirement of 10+ years of experience in EDA software development focused on STA engines.

Responsibilities

Key responsibilities include:

• Architect and develop high-performance STA engines.
• Enhance timing analysis algorithms and improve path search techniques.
• Optimize performance for large IC designs and address runtime bottlenecks.
• Refactor codebases for maintainability and scalability.
• Develop interfaces between STA engines and other EDA tools.
• Support customers during tape-outs and resolve issues based on feedback.

Requirements

Required qualifications include:

• 10+ years of EDA software development experience.
• Deep understanding of STA concepts and algorithms.
• Strong proficiency in C/C++ programming.
• Experience with multi-threading and memory optimization.
• Ability to debug complex issues in large codebases.

Preferred qualifications include:

• Experience with commercial STA tools.
• Knowledge of ASIC/FPGA design flows.
• Background in customer support related to tape-outs.
• Familiarity with distributed computing strategies.

Education Requirements

Not specified.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.