Senior Staff UVM Verification Engineer

Role Overview

We are seeking a Senior Staff UVM Verification Engineer in Nepean, Ontario, Canada. In this role, you will work on complex verification tasks and lead efforts in developing verification methodologies. You will collaborate closely with design teams to ensure high-quality ASIC designs meet performance and functionality standards.

Experience Level

The ideal candidate should have a proven background in ASIC verification, particularly with UVM, coupled with substantial industry experience ideally at a senior level.

Key Responsibilities

• Engage in defining verification strategies for ASIC designs.
• Develop and execute comprehensive test plans utilizing UVM methodology.
• Collaborate with design teams to identify and resolve verification issues.
• Mentor junior engineers to enhance team skills and knowledge.

Essential Requirements

• Bachelor’s or higher degree in Electrical Engineering or related field.
• Extensive experience with UVM and SystemVerilog.
• Strong analytical and problem-solving skills.
• Ability to work effectively in a team-oriented environment.

Education Requirements

A Bachelor’s degree in Electrical Engineering or a related discipline is required. Advanced degrees are preferred but not mandatory. Relevant certifications in verification methodologies are a plus.