Senior Staff System Validation Engineer (FPGA Execution)

Role Summary

The Senior Staff System Validation Engineer will be a key member of the CoreIP team at SiFive, responsible for performing root cause analysis on SiFive cores. This role involves close collaboration with the System Software team to reproduce customer-reported issues and facilitate debugging between hardware and software teams.

Experience Level

Senior

Responsibilities

This role includes the following key responsibilities:

• Owns system-level root cause analysis across processor, SoC, bootloaders, Linux kernel, board, and tools.
• Drives failure triage with customer silicon and decomposes ambiguous failures into testable hypotheses and structured debug plans.
• Works closely with the FPGA team to reproduce failures in the emulation environment.

Requirements

Key requirements for the role are:

• Solid understanding of SoC architectures and experience in chip bring-up or post-silicon verification.
• Deep understanding of Linux kernel internals relevant to silicon debug, including cold/warm bootup flow, exception handling, memory management, and more.
• Experience driving root cause analysis of failures observed at the processor boundary, such as hangs or crashes.
• Proficiency with instruction trace, core debuggers, performance counters, and error logs.
• Ability to collaborate with Design and System SW teams to drive resolution through necessary fixes and workarounds.

Education Requirements

Information not specified.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.