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Senior Staff SOC Engineer - Physical Design

Synopsys
Full-time
On-site
Bengaluru, India
Level - Senior

Role Overview

We are a leading company in the field of chip design, verification, and IP integration, offering innovative solutions that empower technology advancements. As a Senior Staff SOC Engineer specializing in Physical Design at our Bengaluru office, you will play a crucial role in implementing high-performance silicon designs for cutting-edge applications.

Position Summary

The Senior Staff SOC Engineer will be responsible for managing the entire RTL2GDSII physical design flow for advanced technology nodes such as 7nm, 5nm, and 3nm. You will work independently to achieve project deadlines and ensure successful tape-outs. Candidates must have a solid background in physical design automation and collaboration with cross-functional teams.

Experience Level

This role requires a minimum of 8 years of relevant hands-on experience in physical design, particularly with advanced technology nodes. Experience with RTL2GDSII flows and the ability to tackle complex challenges in fast-paced environments is essential.

Key Responsibilities

  • Lead full RTL2GDSII physical design implementations, ensuring quality and performance targets are met.
  • Execute synthesis, detailed place & route, clock tree synthesis (CTS), and static timing analysis (STA).
  • Conduct block-level and full-chip floor-planning, timing closure, EMIR analysis, and physical verification.
  • Collaborate with global teams to solve design challenges and maintain project schedules.
  • Utilize and optimize industry-standard EDA tools like Design Compiler, IC Compiler II, and PrimeTime.
  • Develop automation scripts using scripting languages to enhance design efficiencies.
  • Mentor junior engineers while contributing to the improvement of design methodologies.

Essential Requirements

  • Bachelor’s or Master’s degree in Electronics or Electrical Engineering, or a related field.
  • 8+ years of experience in physical design for advanced technology nodes.
  • Proficient with RTL2GDSII flows and associated tools.
  • Strong scripting skills in Python, PERL, or TCL.
  • Solid understanding of timing constraints and floor-planning techniques.
  • Experience in high-frequency and low-power design methodologies.

Education Requirements

Bachelor's or Master's degree (BE/BTech/MTech) in Electronics, Electrical Engineering, or a related discipline.