Senior Staff SOC Engineer, Physical Design

Role Summary

This position is for a Senior Staff SOC Engineer specializing in physical design. The role focuses on driving the entire RTL2GDSII flow and supporting high-performance silicon chips for advanced technology nodes.

Experience Level

Ideal candidates will possess over 8 years of relevant experience in physical design, particularly with advanced process nodes such as 7nm, 5nm, or 3nm.

Responsibilities

• Independently manage RTL2GDSII physical design implementation, ensuring successful project completions.
• Execute full design flows, including synthesis, place & route, and static timing analysis.
• Conduct block-level and full-chip floor planning and timing closure activities.
• Collaborate with global teams to address complex design challenges promptly.
• Utilize Synopsys EDA tools effectively to achieve optimal design results.
• Develop automation scripts in various programming languages to enhance design processes.
• Contribute to improving design methodologies and mentoring junior engineers.

Requirements

• Bachelor’s or Master’s degree in Electronics or Electrical Engineering or a related field.
• 8+ years of experience in physical design, specifically in cutting-edge technology nodes.
• Hands-on experience with RTL2GDSII flows and proficiency in relevant EDA tools.
• Strong automation and scripting capabilities in languages like Python, PERL, or TCL.
• In-depth understanding of timing constraints and floor planning techniques.

Education Requirements

Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or a closely related field.