Senior Staff RTL Engineer

Role Summary

We are looking for a skilled Senior Staff RTL Engineer to develop and enhance a machine learning engine utilizing low power FPGA technology. The ideal candidate will possess a strong background in RTL design and machine learning applications to execute an efficient implementation of ML operators.

Experience Level

This position requires a significant level of expertise, aiming for candidates with a minimum of 14 years of experience in RTL design, specifically in environments that focus on machine learning and low-power applications.

Responsibilities

The successful candidate will be responsible for:

• Designing and developing RTL for machine learning engines utilizing Verilog and System Verilog-HDL.
• Performing functional simulations using industry-standard simulation tools.
• Architecting efficient hardware for ML operations aimed at low-power FPGA platforms.
• Collaborating with algorithm teams to convert ML models into effective hardware designs.
• Optimizing data paths for high throughput and low latency in processing.
• Implementing image processing and DSP algorithms as needed.
• Managing FPGA/ASIC synthesis flow and timing closure processes.

Requirements

To be considered for this role, candidates should have:

• Deep knowledge of RTL design principles and tools.
• Experience in applying ML operations like convolution in hardware design.
• Familiarity with computer architecture and memory management.
• Additional experience with C and/or SystemC is an advantage.

Education Requirements

A Bachelor's, Master's, or PhD in Electronics, Electrical, or Computer Engineering is necessary, with corresponding years of experience in RTL design as defined above.