Role Summary
This role involves designing and developing algorithms for mixed signal simulation. The engineer will be part of a team focused on enhancing performance in digital and analog/mixed signal simulation.
Experience Level
Senior, requiring 6 to 15 years of relevant experience.
Responsibilities
The key responsibilities include:
- Designing, developing, and troubleshooting core algorithms for simulation.
- Collaborating with local and global teams to enhance performance for GLS and AMS simulation.
- Engaging in technical roles centered on software development and architecture.
- Utilizing knowledge of digital simulation flows and EDA tools to drive innovation.
- Leveraging expertise in Verilog, SystemVerilog, and VHDL to develop cutting-edge solutions.
Requirements
Applicants must have the following skills:
- Strong hands-on experience in C/C++ based software development.
- Deep understanding of design patterns, data structures, algorithms, and programming concepts.
- Knowledge of ASIC design flow and EDA tools and methodologies.
- Proficiency in Verilog, SystemVerilog, and VHDL HDL.
- 6+ years of relevant EDA software experience, preferably in the simulation domain.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

Date Posted: 2026-04-14