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Senior Staff Package Design Engineer - MIS substrate / Flip-chip exposed die (Power/GaN experience required)

Renesas
August 16, 2026
Full-time
On-site
Zhubei, TW
Process Engineering Jobs, Level - Senior

Job Title

Senior Staff Package Design Engineer - MIS substrate / Flip-chip exposed die (Power/GaN experience required)

Role Summary

Design and qualify advanced package and interconnect solutions for power and GaN applications, focusing on MIS substrates and flip‑chip exposed die technologies. The role partners with product, reliability, quality, operations and external OSAT/CM partners to transfer designs into production and to resolve process and quality issues.

Work includes materials and subcontractor selection, DOE-driven process optimization, package qualification, establishing design rules, and supporting production ramp-up for consumer, industrial and automotive power applications.

Experience Level

Senior-level; >10 years of relevant package development experience emphasizing power SiP/module, wafer-level and flip‑chip packaging.

Responsibilities

Accountable for package design, qualification and production transfer for power packaging solutions.

  • Benchmark, select and qualify materials, processes and assembly subcontractors (OSAT) or contract manufacturers (CM).
  • Work with OSAT/CM to run DOE, optimize processes, establish process specifications and resolve production issues.
  • Qualify new packages and processes; coordinate with Product, Reliability, Quality and Operations on customer issues and nonconformances.
  • Ensure smooth production transition and implement ramp-up monitoring.
  • Develop and maintain package design rules and contribute to packaging roadmap execution.
  • Apply statistical process control (SPC) and qualification methods to ensure product quality.

Requirements

Key technical and professional requirements.

Must-have

  • >10 years experience in package development with emphasis on power SiP/modules, wafer‑level and flip‑chip packaging.
  • Proven experience with power packaging or GaN-related package technologies.
  • Strong understanding of assembly processes, qualification methods, and SPC/statistical analysis tools.
  • Experience with DOE and working with OSAT/CM to optimize/process control.
  • Strong interpersonal, communication, analytical and presentation skills.

Nice-to-have

  • Experience with wire‑bonding, multi‑chip module technologies or panel‑level packaging.
  • Experience establishing package design rules and packaging roadmaps.
  • Experience supporting automotive or industrial power application qualifications.

Education Requirements

Doctorate, Master's or Bachelor's degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering.


About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.

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Date Posted: 2026-07-08