Senior Staff Package Design Engineer - MIS substrate / Flip-chip exposed die (Power/GaN experience required)
Design and qualify advanced package and interconnect solutions for power and GaN applications, focusing on MIS substrates and flip‑chip exposed die technologies. The role partners with product, reliability, quality, operations and external OSAT/CM partners to transfer designs into production and to resolve process and quality issues.
Work includes materials and subcontractor selection, DOE-driven process optimization, package qualification, establishing design rules, and supporting production ramp-up for consumer, industrial and automotive power applications.
Senior-level; >10 years of relevant package development experience emphasizing power SiP/module, wafer-level and flip‑chip packaging.
Accountable for package design, qualification and production transfer for power packaging solutions.
Key technical and professional requirements.
Must-have
Nice-to-have
Doctorate, Master's or Bachelor's degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering.
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
