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Senior Staff Package Design Engineer — MIS substrate / flip-chip exposed-die (Power/GaN experience)

Renesas
August 16, 2026
Full-time
On-site
Zhubei, TW
Other Semiconductor Jobs, Level - Senior

Job Title

Senior Staff Package Design Engineer — MIS substrate / flip-chip exposed-die (Power/GaN experience)

Role Summary

Lead design, development, qualification and production transfer of advanced package and interconnect solutions for power SiP/modules, wafer-level and flip-chip packaging. Work across Product, Reliability, Quality and Operations teams and with OSAT/CM partners to ensure manufacturable, high-quality package solutions for industrial, consumer and automotive power applications.

Experience Level

Senior — requires extensive industry experience; posting specifies more than 10 years of relevant package development experience.

Responsibilities

Primary responsibilities include package design, process development and qualification, and production ramp support.

  • Benchmark, select and qualify materials, assembly subcontractors (OSAT) and contract manufacturers (CM).
  • Collaborate with OSAT/CM to plan and run DOE, optimize processes, set process specifications, and resolve issues early in production.
  • Qualify new packages and processes with Product and Reliability teams within required schedules.
  • Manage transitions into production and implement ramp-up monitoring to meet quality and volume targets.
  • Define and maintain package design rules and qualification methods.
  • Contribute to packaging roadmap and maintain technical expertise on power SiP/modules, wafer-level packaging, flip-chip interconnects and panel-level packaging.
  • Work cross-functionally with Marketing, Product, Quality and Operations to address customer issues and support business growth.

Requirements

Must-have technical experience and skills; preferred items noted separately.

  • Extensive hands-on experience (posting specifies >10 years) in package development with emphasis on power SiP/module, wafer-level and flip-chip packaging.
  • Strong understanding of assembly processes, qualification methods, and statistical process control (SPC) and analysis tools.
  • Proven experience running DOEs and optimizing manufacturing processes with OSATs/CMs.
  • Strong analytical, presentation, interpersonal and communication skills; able to work cross-functionally.
  • Ability to lead production transfer, ramp-up monitoring, and resolve process issues to meet product quality requirements.
  • Knowledge of wire-bonding and multi-chip module technologies is a plus.
  • GaN-related packaging is preferred (the posting highlights power expertise and mentions GaN as an advantage).

Education Requirements

Doctorate, Master’s or Bachelor’s degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering.


About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.

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Date Posted: 2026-07-08