Senior Staff Hardware Engineer - ASIC Implementation
Arycs TechnologiesJob Title
Senior Staff Hardware Engineer - ASIC Implementation
Role Summary
Lead digital implementation for DSP ASIC programs, providing hands-on technical leadership across RTL, synthesis, and backend implementation to achieve successful first-pass silicon delivery.
The role requires coordinating internal engineering teams and external backend vendors to drive timing, power, and integration closure for tapeout-ready designs. Positions are based in Los Gatos, CA or Cleveland, OH with onsite implementation activities.
Experience Level
Senior — typically requires 10+ years of ASIC digital implementation experience and proven tapeout delivery.
Responsibilities
Primary responsibilities focus on RTL-to-GDS implementation, timing and power closure, and vendor coordination.
- Perform and debug lint, CDC, and RDC checks; develop automation and analysis scripts.
- Drive RTL-to-synthesis implementation flows and develop supporting automation.
- Create and maintain timing constraints (SDC) and perform static timing analysis for timing closure.
- Conduct synthesis for design exploration and PPA optimization.
- Maintain power intent (UPF) and support low-power implementation and RTL power analysis.
- Analyze timing reports, identify violations, and coordinate RTL or implementation fixes.
- Lead design readiness reviews and serve as the primary technical interface with external backend teams.
- Oversee place-and-route activities, review backend metrics, and track resolution of physical design issues.
- Support gate-level power/timing correlation and guide closure strategies through tapeout.
- Coordinate schedules, risks, and implementation activities across internal teams and external partners.
Requirements
Required technical skills and experience to perform the role.
Must-have:
- 10+ years of ASIC digital implementation experience, including tapeout support.
- Strong experience with RTL-to-synthesis flows (e.g., Design Compiler, Fusion Compiler).
- Deep understanding of static timing analysis and timing closure tools (e.g., PrimeTime).
- Experience with UPF-based low-power implementation and RTL power analysis tools (e.g., PrimePower, RTL Architect).
- Experience debugging post-layout timing and working with backend implementation vendors.
- Strong scripting skills for automation and analysis (Tcl, Python).
Nice-to-have:
- Experience with high-throughput datapath or DSP-focused designs.
- Familiarity with advanced process nodes (7 nm and below).
- Experience with place-and-route and physical design flows.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field as listed in the source. (Education specified: Bachelor's or Master's in EE, CE, or related field.)
About the Company
Company: Arycs Technologies
Headquarters: Los Gatos, CA, USA
ASIC design and hardware engineering firm specializing in DSP ASIC development and digital implementation services. Provides RTL-to-tapeout support, timing and power closure, and collaboration with backend vendors for silicon delivery.
