Senior Staff Engineer, RTL Design and Verification

Role Summary

The Senior Staff Engineer in RTL Design and Verification is responsible for the design and verification of advanced Silicon Lifecycle Management (SLM) IPs. This role involves collaborating with cross-functional teams to tackle challenges in chip design and improve verification methodologies.

Experience Level

We are looking for candidates with 8+ years of hands-on experience in RTL design and verification, with a strong grasp of chip design environments and verification tools.

Responsibilities

The core responsibilities include:

• Designing and verifying RTL for advanced SLM IPs, focusing on next-generation 3D-IC technology.
• Developing comprehensive test cases to verify product functionality and performance.
• Engaging with both internal teams and customers to resolve technical issues through debugging and analysis.
• Keeping up with the latest trends in SLM and 3D-IC technologies.
• Documenting design specifications and verification plans for clarity and continuity.
• Participating in code reviews and technical discussions to foster innovation.

Requirements

The ideal candidate will possess:

• BS/MS in Computer Science, Electrical Engineering, or a related field.
• Thorough knowledge of EDA tools, Verilog, System Verilog, and Formal Verification methodologies.
• Experience in Unix/Linux operating systems.
• Excellent problem-solving skills, particularly in difficult chip design scenarios.
• Strong communication skills in English, both written and verbal.
• Knowledge of mixed-signal design is advantageous.
• Familiarity with 3D-IC standards and semiconductor verification practices.

Education Requirements

A Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field is required.