Senior Staff Engineer, RTL Design and Verification (R&D Engineering)
Responsible for RTL design and verification of Silicon Lifecycle Management (SLM) IPs, including next‑generation 3D‑IC projects. Collaborates with internal teams and customers to deliver reliable semiconductor IP and integration guidance.
Focuses on verification methodology, automation, debugging, documentation, and improving product quality and performance.
Senior — typically 5+ years of hands-on RTL design and verification experience.
Core responsibilities include design, verification, and cross-team collaboration:
Must-have technical skills and experience:
BS or MS in Computer Science, Electrical Engineering, or a related field (as stated in the posting). The posting does not explicitly state an alternative equivalence to degree requirements.
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
