Senior Staff Engineer, Physical Design

Job Title

Senior Staff Engineer, Physical Design

Role Summary

Lead physical implementation of UCIe PHY blocks and testchips through floorplanning, placement, timing closure, and tapeout on leading-edge process nodes. Work on a cross-functional engineering team that owns PPA and signoff quality for connectivity IP used in AI accelerators and high-performance compute systems.

Expected to drive technical decisions, collaborate with verification/DFT/integration teams and foundry partners, and mentor junior engineers to improve design cycle time and silicon quality.

Experience Level

Senior — 7+ years of hands-on ASIC physical design experience.

Responsibilities

Primary ownership and execution responsibilities for physical design and delivery of IP/testchips:

• Own physical implementation from floorplanning through GDS for UCIe PHY blocks and testchips on 5nm and advanced nodes.
• Drive synthesis, placement, routing, timing closure, and physical verification using DC, PT, ICC2/FC, and ICV across concurrent projects.
• Coordinate with verification, DFT, and IP integration teams to resolve design and timing issues and meet PPA targets on schedule.
• Lead design reviews, produce tradeoff analyses, and make real-time decisions on floorplan, clocking, and signoff strategies.
• Pilot and document new physical design flows and advanced-node methodologies for team adoption.
• Mentor and train junior engineers on timing closure, physical verification, and toolchain best practices.
• Work with foundry and customer engineering teams to resolve technology-file, DRC/LVS, and silicon bring-up issues.

Requirements

Required skills and experience; listed as must-have first, with a few valuable additions.

• Must-have: 7+ years of hands-on ASIC physical design experience with ownership of synthesis, P&R, timing closure, and physical verification.
• Must-have: Multiple tapeouts and signoffs in 5nm or more advanced process nodes; experience taking designs to GDS.
• Must-have: Strong proficiency with industry tools: Design Compiler (DC), PrimeTime (PT), ICC2/Foundry Compiler (FC), and ICV (or equivalent flows).
• Must-have: Proven track record on SoC or IP tapeouts where you owned significant portions of the physical design and were accountable for signoff.
• Must-have: Deep understanding of FinFET-era challenges (multi-patterning, EM, IR drop) and advanced-node physical design tradeoffs.
• Nice-to-have: Experience with DFT insertion, scan routing, ATPG and debugging DFT-related timing/physical issues.
• Nice-to-have: Exposure to UCIe, SerDes, or other high-speed interface IP.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.