Senior Staff Engineer – ASIC Physical Design

Role Overview

This position is for a Senior Staff Engineer specializing in ASIC Physical Design at Synopsys. The role involves leveraging cutting-edge technology to support the development of high-performance silicon chips and software content.

Summary of Duties

The primary responsibility is to develop a comprehensive front-to-back end design implementation methodology utilizing Synopsys tools. The engineer will engage in multiple tasks to optimize design processes including Timing Analysis, Power Analysis, and more, ensuring best practices in digital design methodologies.

Required Experience Level

The candidate should have over 10 years of hands-on experience in ASIC digital implementation, specifically with high-speed digital IP cores and SOCs development.

Key Responsibilities

Responsibilities include:

• Developing design methodologies for full design implementation from RTL to GDSII.
• Engaging with design teams to enhance performance and efficiency through collaborative efforts.
• Evaluating design processes including synthesis, place and route, and timing/power optimization.
• Creating and maintaining documentation, scripts, and training related to digital design practices.
• Initiating continuous improvements in design methodologies and tools.

Essential Skills and Qualifications

Applicants should possess:

• A BS or MS in Electrical Engineering with over 10 years of relevant experience.
• Strong knowledge of ASIC design flows, IP deliverables, and physical design tools.
• Experience with Fusion Compiler or similar synthesis tools.
• Strong problem-solving skills and ability to communicate effectively across teams.
• Familiarity with Synopsys tools and high-speed interface protocols is an advantage.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering is required.