Senior Staff Engineer - ASIC Digital Design

Role Summary

The position involves leading the design and implementation of complex ASIC and FPGA designs. You will work on various aspects of digital design, including architecture, RTL coding, verification, synthesis, and timing closure. The role requires collaboration with cross-functional teams to ensure that designs are optimized for performance, power, and area.

Experience Level

This is a Senior level position, requiring extensive experience in ASIC digital design methodologies and practices.

Responsibilities

• Lead the design and implementation of digital systems from specification to completion.
• Collaborate with architecture and ISP teams to define design specifications.
• Carry out RTL coding, verification, and timing closure.
• Conduct design reviews to ensure adherence to best practices and quality standards.
• Mentor junior engineers on digital design principles and practices.

Requirements

Must have proven experience in ASIC digital design with a strong understanding of RTL design and verification tools. Proficiency in Verilog/System Verilog and familiarity with ASIC flow tools is essential. Strong problem-solving skills and the ability to work effectively in teams are required.

Education Requirements

A Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field is required.