Senior Staff Design Verification Engineer

Role Summary

The Senior Staff Design Verification Engineer is responsible for developing verification plans based on chip specifications and setting up digital verification flows. This position focuses on ensuring spec compliance, designing optimized digital blocks, and mentoring junior engineers.

Experience Level

Senior, requiring 10+ years of experience in Digital Verification and UVM.

Responsibilities

Key responsibilities include:

• Develop verification plans based on chip specifications.
• Set up Digital Verification flow for Full Chip from scratch.
• Design and develop verification systems, focusing on reuse and scalability.
• Design optimized digital blocks meeting functional and low power constraints.
• Develop TCL scripts for synthesis, DFT insertion, and static timing analysis.
• Support DFT strategy and implementation.
• Develop verification test cases and interface with P&R for digital hand-off.
• Produce high-quality documentation for verification procedures.
• Mentor and train junior digital verification engineers.

Requirements

Qualifications include:

• 10+ years experience in Digital Verification and UVM.
• Hands-on experience with Verilog/System-Verilog.
• Experience in logic design, micro-architecture, and RTL coding.
• Knowledge of verification methodologies and techniques.
• Experience with mixed-signal integrated circuits preferred.
• Excellent communication skills and ability to work independently.

Education Requirements

Not specified.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.