Senior/Staff Design Verification Engineer - Coherent Interconnect

Role Summary

The ARM Neoverse Coherent Mesh Network is a highly scalable and configurable system interconnect used in various applications including networking infrastructure and high performance compute. We are looking for design verification engineers to help in developing our next generation products.

Experience Level

7+ years of experience in verification or RTL design is required, with expertise in microarchitecture desired.

Responsibilities

• Build and maintain detailed verification plans and strategies.
• Collaborate with architects and designers to debug and develop new features.
• Architect and develop SystemVerilog/UVM based test benches.
• Create new stimulus and coverage and debug functional regression failures.
• Drive improvements in verification methodology.

Requirements

Education: Bachelor's, Master's, or PhD in Electrical/Computer Engineering or Computer Science.

• 7+ years of hands-on experience in verification/RTL design.
• Experience with CPU microarchitecture, cache coherence, memory systems, and bus protocols (e.g., AMBA CHI, ACE).
• Previous experience with System Verilog/UVM constrained-random test benches.

Education Requirements

Bachelor's, Master's, or PhD in Electrical/Computer Engineering or Computer Science.