Senior Staff Design Verification Engineer - Coherent Interconnect

Role Summary

The Senior Staff Design Verification Engineer role at Arm focuses on the ARM Neoverse Coherent Mesh Network, which is integral to a variety of applications including networking, storage, server solutions, and AI. Candidates will play a key role as design verification engineers contributing to the development of next-generation products.

Experience Level

This position requires an advanced level of expertise with at least 7 years of hands-on experience in verification or RTL design, showcasing deep knowledge of CPU microarchitecture and complex verification methodologies.

Responsibilities

• Develop and maintain comprehensive verification plans and strategies for our products.
• Collaborate with architects and designers to debug features while managing multiple partnership needs throughout the product development process.
• Design and implement efficient SystemVerilog/UVM test benches.
• Create new stimuli and coverage metrics while addressing functional regression failures to ensure complete coverage.
• Initiate and advocate for enhancements in verification methodologies.

Requirements

Candidates should possess a Bachelor's, Master's, or PhD in Electrical/Computer Engineering or Computer Science, alongside 7+ years in verification/RTL design, particularly with CPU microarchitecture knowledge. Experience with System Verilog/UVM test benches, cache coherence, and memory systems is essential. Nice to have skills include familiarity with PCIe, Compute Express Link, and formal verification techniques.

Education Requirements

Bachelor's, Master's or PhD in Electrical/Computer Engineering or Computer Science is required for this role.