Senior Staff Design Engineer - PCIe/CXL Subsystem COE

Job Title

Senior Staff Design Engineer - PCIe/CXL Subsystem COE

Role Summary

Design, implement, and deliver PCIe/CXL IP subsystems used across Marvell SoCs. Work within the Center of Excellence to define subsystem micro-architecture, produce production-ready RTL, and ensure integration, verification, and silicon bring-up across cross-functional teams.

Experience Level

Senior — typically requires 8–10+ years of relevant RTL and subsystem design experience.

Responsibilities

Key responsibilities include owning subsystem design and collaborating across architecture, verification, physical design, firmware, and validation teams.

• Define and drive PCIe/CXL subsystem micro-architecture and RTL implementation.
• Translate architecture requirements into robust RTL designs and integrations.
• Collaborate with design verification on test plans, debug, and coverage closure.
• Work with Physical Design and DFT teams to ensure PD-friendly and DFT-ready RTL.
• Support silicon bring-up and post-silicon debug with firmware and validation teams.
• Improve design quality, enforce coding best practices, and promote reuse.
• Participate in design and milestone reviews and cross-functional technical discussions.
• Mentor and provide technical leadership to junior designers.

Requirements

Must-have technical skills and experience.

• Proven experience delivering complex PCIe/CXL controllers or subsystems from architecture through RTL closure.
• Strong hands-on experience in SystemVerilog / Verilog RTL development.
• Familiarity with PCIe and CXL specifications.
• Experience with ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE).
• Deep understanding of clocking, resets, CDC/RDC, low-power techniques, and performance optimization.
• Experience supporting lint, CDC/RDC analysis, synthesis, and design sign-off flows.
• Experience with industry-standard EDA tools (Synopsys, Cadence, Mentor/Siemens).
• Proficient in scripting (TCL, Perl, Python) and version control systems (Git, SVN).

Nice-to-have:

• End-to-end PCIe/CXL subsystem RTL design execution and sign-off experience.
• Experience designing high-performance, low-latency data paths and handling ordering, coherency, and error mechanisms.
• Proficiency debugging functional and performance issues at subsystem and SoC levels.
• Familiarity with post-silicon bring-up and debug methodologies.
• Prior mentoring and cross-functional technical leadership experience.

Education Requirements

Bachelor's or Master's degree in Electronics / Electrical Engineering or a related technical field, or equivalent practical experience. The posting notes an expectation of roughly 8–10+ years of relevant experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.