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Senior Staff ASIC Digital Design Engineer

Synopsys
October 8, 2026
Full-time
On-site
Hyderabad, Telangana, India
RTL Design Jobs, Level - Senior

Job Title

Senior Staff ASIC Digital Design Engineer

Role Summary

Lead architecture and implementation of high-performance RTL for ASIC IP cores, focused on die-to-die and high-speed communication protocols for automotive and consumer applications. Work within a multi-site design team, mentor engineers, and coordinate with verification and customers to deliver production-quality silicon IP.

Contribute technical leadership to accelerate delivery of next-generation communication IP.

Experience Level

Senior-level - typically 12+ years of ASIC digital design experience with demonstrated technical leadership in RTL and micro-architecture.

Responsibilities

Primary responsibilities include:

  • Architect and define micro-architectures; produce architecture and micro-architecture documentation from functional specifications.
  • Implement RTL (Verilog/SystemVerilog) and execute synthesis, CDC analysis, formal checks, and static timing activities.
  • Collaborate with verification to plan, execute, and close verification cycles; develop and support test strategies.
  • Debug designs, optimize for P&R-aware synthesis and high-speed operation, and support bring-up and productization activities.
  • Engage with customers to clarify requirements and ensure design alignment with end-user needs.
  • Mentor and technically lead a global, multi-site team of designers to improve quality and delivery.

Requirements

Must-have skills and experience:

  • Strong RTL coding in Verilog/SystemVerilog and micro-architecture design expertise.
  • Experience with high-speed and die-to-die communication protocols such as UCIe, Ethernet, PCIe, DDR, CXL, USB, MPHY, UFS, UNIPRO, or similar.
  • Hands-on experience with synthesis, CDC analysis, formal verification, and static timing analysis; familiarity with P&R-aware synthesis flows.
  • Familiarity with physical synthesis/place-and-route tools such as Fusion Compiler or equivalents.
  • Experience with revision control systems (e.g., Perforce) and scripting (Perl, Shell) for automation.
  • Exposure to IP design quality processes and demonstrated ability to lead and mentor design teams.

Education Requirements

BSEE or MSEE in Electrical Engineering is specified in the source posting.


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-10-06