Senior/Staff ASIC Design Verification Engineer

Role Summary

The Senior/Staff ASIC Design Verification Engineer is responsible for developing and executing verification strategies for ASIC designs. This role involves working closely with design engineers to ensure thorough testing and validation of complex digital circuits.

Experience Level

Senior level, typically requiring over 5 years of experience in ASIC design verification.

Responsibilities

The key responsibilities include:

• Developing and implementing verification plans for ASIC projects.
• Working collaboratively with design teams to define verification requirements.
• Executing simulations and analyzing verification results to ensure compliance with specifications.
• Debugging issues found during verification and reporting findings.
• Mentoring junior engineers in best practices for design verification.

Requirements

Must-have qualifications include:

• Bachelor's or Master's degree in Electrical Engineering or related field.
• Proficiency in SystemVerilog, UVM, or similar verification methodologies.
• Strong understanding of digital design concepts and ASIC development lifecycle.
• Experience with simulation tools and debugging methodologies.
• Excellent problem-solving and communication skills.

Education Requirements

A degree in Electrical Engineering or a related field is required.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.