Senior Staff ASIC Design Verification Engineer

Job Title

Senior Staff ASIC Design Verification Engineer

Role Summary

The Senior Staff ASIC Design Verification Engineer works within the design team to develop high-speed mixed-signal PHY IPs. This role involves RTL and Gate-Level Simulation (GLS) verification for mixed-signal designs and executing verification plans and strategies.

Experience Level

Senior level, with a minimum of 2 years of relevant experience in ASIC RTL design flow.

Responsibilities

The key responsibilities include:

• Collaborating with digital design teams for the development of high-speed mixed-signal PHY IPs.
• Participating in RTL and Gate-Level Simulation (GLS) verification.
• Defining, developing, and executing functional verification plans and test strategies.
• Conducting RTL and SDF-annotated gate-level simulations using UVM-based methodologies.
• Generating VCD files and performing power analysis/reporting using PrimeTime PX.

Requirements

Must-have skills and experience:

• Minimum 2 years of experience in ASIC RTL design flow.
• Proficiency in RTL and GLS verification with strong debugging capabilities.
• Excellent teamwork and communication skills, with professional proficiency in English.
• Strong knowledge of high-speed interface protocols (e.g., DDR, HBM, PCIe PHYs) is a distinct advantage.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.