Senior Staff Analog Mixed Signal Design Engineer

Role Overview

The Senior Staff Analog Mixed Signal Design Engineer position focuses on designing and verifying high-speed and optical transceivers for communication infrastructure. This role involves collaboration with a team to implement architectures for various circuits, ensuring high-performance standards are met while utilizing industry-standard verification tools.

Position Summary

The candidate will engage in architectural investigations and design implementations for circuits, such as PLLs, ADCs, amplifiers, and various other components, to meet key performance metrics. The successful individual will interact with layout, verification, and application teams, leading to the successful transition from concept to production of analog IP.

Experience Level

This role is classified as Level - Senior and requires a minimum of 5 years of experience in the field of Electrical Engineering or related domains.

Job Duties

The responsibilities include but are not limited to:

• Conducting architectural investigations and implementation of circuits like PLL, DLL, ADC, and others.
• Performing design verification using tools such as SPICE, Spectre, and MATLAB.
• Collaborating with cross-functional teams to deliver analog IP through all development stages.
• Experience in system-level pre-tape out analog validation and lab chip bring-up activities.
• Leading and communicating effectively within a team of analog design engineers.

Essential Qualifications

The ideal candidate should have:

• A Master's degree and/or PhD in Electrical Engineering or a related field.
• Proficiency in designing PLLs, Data Converters, and high-speed SerDes.
• Expertise in analog design and verification tools, particularly Virtuoso, Spectre, and ADE.
• Knowledge surrounding signal integrity improvement, noise reduction, and clock generation.
• Strong background in analog layouts, particularly in FinFET designs.

Education Requirements

Master's or PhD in Electrical Engineering or related areas.